Improving lithography performance with advanced control loops fueled by integrated metrology

Lithography complexity and performance requirements increase with each technology node. New patterning techniques such as multi-patterning generate additional challenges and accelerate the demand for better overlay, CD and focus control. For sure advances of process tools are substantial, but ultimate performance can only be achieved by improving the system in a holistic way.

Importance of metrology is the first key element in the improvement cycle. For overlay measurements image based methods have dominated the industry for many years.  Now advanced technology nodes are adapting diffraction based overlay metrology. The build-in self calibration and the much more device-like target design of the used measurement structures provide better accuracy and process robustness, which will result as better on-product overlay. Furthermore, computational target design enables prediction of accuracy and robustness, thus opens further optimization opportunities. For both recent data will be reported.

Gathering more key index information allows “finer” control and enables better performance, but have to be balanced with economical and logistical limits. Getting information immediately after wafer processing limits “in-risk” WIP in case of tool excursions. Both are strong arguments for integrated metrology. Consequently Yieldstar has also been rolled-out as photo cluster integrated metrology unit and much focus has been given on managing cluster throughput and reliability concerns.

At the end of the first chapter recent data of the CD and focus measurement capabilities of our 3-in-1 metrology unit will be shared and an outlook on potential benefits will be given.

As importance of holistic improvements has been stressed, the second part dedicates on enhanced tool interfaces/capabilities and new control algorithms. On practical example wafer edge non-uniformity control is described. The application itself is not new. Wafer edge non-uniformity has challenged engineers for years. However recent made hardware and software algorithm improvements have greatly extended control capabilities. It will be shown how those can be utilized to significantly reduce process variations especially at the wafer edge.

 

Curriculum Vitae

In 1994, after completion of his Electrical Engineering study at the Technical University Dresden, Steffen joint semiconductor industry. Since that he enjoys mastering challenges and driving new developments in the lithography, metrology and process integration area.

He managed various projects in Asia and Europa, was e.g. in charge of ramping-up lithography at the new 300mm Inotera Memories fab  in Taiwan or did drive double patterning technology development from basic research into pilot production at Qimonda Dresden.

In 2009 he moved to ASML taking over responsibility of the YieldStar metrology platform field testing and mass production introduction in Taiwan. Upon completion of the project he moved back to Europa in late 2013, coaching now worldwide YieldStar rollout teams and is working on new product introductions.