At a Crossroads in Scaling"

The nanoelectronics industry has enjoyed decades of productivity gains driven by lithographic scaling. However, starting around the first decade of the 21st century, scaling slowed due to delays in the introduction of extreme ultraviolet (EUV). A multitude of new materials were introduced, a pace that continues unabated and which helps to drive increases in performance or reductions in power consumption. However, to maintain the pace of die-level cost reduction, a different set of approaches have been proposed, only one of which is to use EUV. Two other approaches are being pursued vigorously, a transition in wafer size to 450mm and chip stacking, a.k.a. 3D scaling. All three approaches face the challenge of becoming cost-effective prior to wide-spread adoption.

Announced by New York Governor Andrew M. Cuomo in September 2011, the Global 450 Consortium (G450C) is a first-of-its-kind collaboration headquartered and housed at the SUNY College of Nanoscale Science and Engineering (CNSE), comprised of five leading international companies working to create the next generation of computer chip technology: Intel, Samsung, TSMC, IBM and GlobalFoundries. The goal of G450C is to support the smooth and coordinated industry transition from 300mm wafer to 450mm wafer production, leveraging industry and government investments to demonstrate and deploy 450mm wafer tools and process capabilities.

The first generation of EUV production scanners are currently being delivered. One such scanner is being installed at CNSE with the goal of start of development activities in 2Q2014. The scanner will be used by a consortium of companies around IBM for development of sub-10nm technology node CMOS, as well as in partnership with SEMATECH to support advanced resist and mask development.

Chip stacking technologies, either via interposers (“2.5D”) or chip stacks (“3D”), are being developed by a wide range of R&D organizations and companies world-wide. No standard integration scheme has emerged yet due to constraints in yield management or limitations in equipment cost of ownership.

The presentation will mention equipment and control challenges associated with all three approaches.  The programs at CNSE are working closely with SEMI and F450C on the development of factory integration and wafer standards. CNSE and its partners will support suppliers working jointly on opportunities such as standardization of subsystems and facilities/installation components to reduce costs and lead times. Lastly, the talk will touch upon the challenge of “big data” and data management driven by the complexity of today’s processes, tooling and associated control schemes.

Curriculum Vitae

As CNSE Executive Vice President of Innovation and Technology, Michael Liehr focuses on the creation of new business opportunities and manages integrated industry-university consortia and public-private partnerships. He is also responsible for the effective and efficient operation of the CNSE core strategic semiconductor and packaging partnership engagements, including the IBM, GLOBALFOUNDRIES, SEMATECH, AMAT, TEL, and LAM partnerships.

Prior to this assignment, he led the Global 450mm Consortium through the start-up phase as the General Manager. Dr. Liehr is further the Vice President for Research at the College of Nanoscale Science and Engineering in Albany, NY.  Prior to joining CNSE, Dr. Liehr served as an IBM executive responsible for Worldwide Semiconductor Manufacturing Strategic Production Alliances for leading-edge semiconductor products.