Keynote Speakers

Roberto Zafalon - STMicroelectronics

Keynote 1

“The Renaissance of Nanoelectronics and Smart Systems industry: More than Moore in the Italian eco-system”

We’ll look at the new process for discovery the best innovation and growth opportunities in the field of Nanoelectronics’ More than Moore: a key enabling technology where the Italian eco-system is fostering the new Renaissance of semiconductor industry. A Life to Discover!


Curriculum Vitae

Dr. Roberto Zafalon is EU Technology Programmes Director - Italy, in charge to foster and leverage the link between ST technology groups and the R&D cooperative EU programs. at STMicroelectronics, Agrate Brianza (Milano), Italy.
In his current capacity since July 2007, he elaborates the vision and roadmap, seeks for project financing and drives industrial R&D teams to pursue innovative solutions in the field of embedded systems and nanoelectronics, for corporate product divisions and labs. He is with STMicroelectronics (one of world’s top 5 semiconductor firms) since 25 years.

He is Steering Board member of ARTEMIS-IA and EPOSS (the European Technology Platform on Smart Systems Integration) and member of AENEAS working groups. He currently is, and has been in the past, General Project Manager and Coordinator of major Integrated Projects under FP6, FP7 and JTI calls 2009-2013, including KET Pilot Lines.  He has been selected by FP7-ICT and ARTEMIS JU as independent expert to review the project submitted to some past calls.

From 2000 until June 2007, he has been the head of the Competence Center for Low Power System Design at the Advanced System Technology, the ST’s Corporate System R&D group. The main targets have been the next generation's embedded systems trade-offs,  including algorithmic and architectural design exploration and power optimization, SW/HW partitioning and RF optimization and co-verification, power profiling, estimation and macro-modeling, energy efficient Network on Chip and RT-OS featuring dynamic power management policies.
As far as the on-chip communication is concerned, shared bus interconnects represent only a partial, short-term solution, because of their limited scalability. We focus on parallel and  scalable interconnect architectures to support the rapidly growing  communication bandwidth’s requirement, both in terms of Low Power Multi Processor Platforms and Energy Efficient NoC’s.